As high performance integrated circuits (e.g., very large scale integration, VLSI circuits) advance, the power consumed by these circuits is of greater concern. Power consumption was addressed during the logic synthesis of previous technology nodes by tuning the threshold voltage (Vt) of each cell in the circuit to a desired frequency, and using high-cost cooling systems to regulate the heat generated by the circuitry including those cells. However, as these VLSI devices advance, they reduce in size, thereby increasing their power dissipation per square unit, which contributes to overheating.
Multi-threshold voltage (Multi-Vt) library cells have been implemented in the logic synthesis process to address both performance and power consumption. These Multi-Vt library cells can be set at different threshold voltage levels, e.g., level 1 (vt1), level 2 (vt2), or level 3 (vt3). Traditionally, circuit models have been designed to limit the percentage of Multi-Vt cells operating at low Vt (e.g., vt1), as these low Vt cells draw more leakage power than the other Vt cells (e.g., vt2 or vt3). Additionally, this conventional approach has included switching all non-critical gates to higher Vt levels (e.g., vt3) to further reduce leakage power.
This focus on leakage power still fails to adequately account for the heat dissipated by each cell, and may still produce a circuit prone to overheating. This leakage power-focused approach also does not account for other power contribution factors like dynamic power and glitch power.